The invention relates to an efficient topography for a sixteen bit CMOS microprocessor chip having the capability of either operating as a sixteen bit microprocessor or operating to emulate the well-known 6502 eight bit integrated circuit microprocessor, depending only on the state of a software "emulation bit" or "E" bit.
Those skilled in the art of integrated circuit design, and particularly microprocessor chip design, know that the size of a high volume integrated circuit chip is a dominant factor in the ultimate yield and manufacturing cost per unit. In all of the integrated circuit technologies, including the CMOS technology, large scale integrated (LSI) chips such as microprocessor chips include thousands of conductive lines and P-channel MOSFETS (metal-oxide-semiconductor field effect transistors) and N-channel MOSFETS. Some of the lines are composed of aluminum metal interconnection layers and others are composed of polycrystalline silicon interconnection layers on different insulative layers, and others of the conductors are diffused conductors. Certain minimum line widths and spacings between the respective lines and the sources and drains of the MOSFETS must be maintained to avoid short circuits and parasitic effects despite slight variations in the manufacturing processes due to presence of minute particulates that are invariably present in the semiconductor manufacturing facilities. Due to the low current supplying capability of the very small MOSFETS that must be used in order to achieve high functional density of the integrated circuits, the lengths of the interconnecting lines and their associated capacitances must be minimized, not only to reduce chip size, but also to achieve maximum circuit operating speeds. A wide variety of design trade-offs, including the necessity to minimize chip size, obtain a suitable chip aspect ratio (which enhances integrated circuit chip yield and wire bonding yield), increase circuit operating speeds, reduce power consumption, and achieve acceptable reliability all are involved in obtaining an optimum "layout" or topography of the MOSFETS and the interconnection patterns therebetween are required in order to obtain an integrated circuit which is both economical and has acceptable operating characteristics.
Some of the numerous design constraints faced by the MOS, LSI chip designer include specifications for minimum widths and spacings of diffused regions in the silicon, minimum widths and spacings for metal interconnection lines, the minimum size required for polycrystalline silicon conductors, the minimum size required for contact openings in the insulating "field" oxides, the spacings required between the edges of contact openings to the edges of the diffused regions or polycrystalline silicon regions, the fact that polycrystalline silicon conductors cannot cross over each other or over diffused regions in most silicon gate manufacturing processes, and the constraint that conductors on the same layer of insulating oxide cannot cross over like conductors.
Furthermore, the high amount of capacitances associated with diffused regions and the high resistances of both diffused regions and polycrystalline silicon conductors must be carefully considered by the circuit designer and also by the chip designer in arriving at an optimum chip topography For many types of circuits, such as the microprocessor of the present invention, an extremely large number of conductive lines between sections of logic circuitry are required. The practically infinite number of possibilities for routing the various conductors and placing of the various MOSFETS taxes the skill and ingenuity of even the most resourceful chip designers and circuit designers (and is far beyond the capability of the most sophisticated computer layout programs yet available). Other constraints faced by the chip layout designer and the circuit designer involve the need to minimize cross-coupling and parasitic effects which occur between various conductive lines and conductive regions. Such effects may degrade voltages on various conductors, leading to inoperative circuitry or low reliability operation under certain operating conditions.
The technical and commercial success of an electronic product utilizing MOSLSI technology hinges on the ability of the chip designer to achieve an optimum chip topography. It is well known that a very high level of creative effort is required, usually both by circuit designers or layout draftsmen, to achieve a chip topography or layout which enables the integrated circuit to have acceptable operating speeds and low power dissipation and yet is sufficiently small in chip area to have a high chip per wafer yield, i.e., to be economically feasible. Often, many months of such effort between chip designers and circuit designers result in numerous trial layout designs and redesigns and concomitant circuit design revisions before a reasonably optimum topography for a single MOSLSI chip is achieved. Often, until a particular new overall insight or approach is conceived for a particularly difficult, complex, and large functional subsection of an integrated circuit chip, such as an instruction decoding subsection in a microprocessor, is arrived at, the desired chip is clearly economically unfeasible. It is on the basis of such an insight that the eight bit CMOS chip topography described in the above-mentioned parent application became economically feasible, resulting in a CMOS that has become a commercial success. It is on the basis of another such insight, arrived at after over a year of design and layout experimentation, that the sixteen bit CMOS microprocessor layout of the present invention could be reduced to a size that made the chip size commercially practical and resulted in adequate operating speed.
Although various single chip microprocessors, such as the 6502, the 6800, the 68000, the 8088, the Z80, and others have been widely used, all of them have various shortcomings from the viewpoint of a computer system designer trying to design a low cost computer system because of the inconvenience of implementing certain functions. Some of the functions that are difficult to implement using prior single chip microprocessors include the problems of efficiently using program memory, i.e., typically slow ROM (read-only memory), in which the program is stored and data memory, i.e., high speed memory in which intermediate data results are stored, dealing with abort conditions such as invalid addresses, which requires aborting the present instruction, executing an abort subroutine, and then re-executing an entire subroutine in which the aborted instruction was contained.
Another problem that is faced by computer designers using prior single chip microprocessors is the need to have new software written for computers that use newly developed, faster microprocessors with greater computing power. It would be very desirable to provide a technique by means of which newer microprocessors, such as 16 or 32 bit microprocessors, can execute already available software written for previous single chip microprocessors having fewer bits in their data words, fewer instructions, and generally less computing capability.